Cadence CONFORMAL 15.20.1 Linux版

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Cadence CONFORMAL 15.20.1 Linux版
  • 软件作者: 网络搜集
  • 软件大小: 555 MB
  • 下载次数: | 所属栏目: 电子电路
  • 软件语言: 英文软件
  • 需要金币: 40 金币 金币充值金币
  • 软件评级: ★★★★★
  • 更新时间: 2016-10-09
  • 软件授权: 破解软件
  • 插件情况:
  • 运行环境: RHEL5 6 7 SLES11 IBM AIX 6.1 7
Cadence设计系统公司,在全球电子设计创新领先企业,已经发布的Cadence CONFORMAL 15.20 版本,支持RHEL 5, RHEL 6, RHEL 7, SLES 11.0, IBM AIX 6.1和7.1系统。该技术为您提供一个独立的等效验证解决方案,使设计的验证从RTL到从P&R的最终网表。
 
除了标准的等效性检查,共形解决方案提供:
 
- 低功耗设计静态验证解决方案,包括低功耗感知等效检查
- 最少的网表的变化和更快的出带ECO自动生成功能
- 约束设计师跨时钟域和SDC验证解决方案
 
Cadence的约束形设计提供了开发和管理的约束和时钟域交叉(疾病预防控制中心)一套完整高效的路径,以确保它们在功能上是正确的从RTL到布局。通过快速,准确地查明真正的设计问题,提供更高质量的时序约束,寻找具有时钟域同步的问题,该解决方案可以帮助您降低整体的设计周期,提高硅片质量的复杂的SoC设计。
 
随着形约束Designer中,可以通过约束的正式确认减少返工的风险。由于该解决方案很快验证失败的时序路径在功能上假的,它加快了时序收敛收敛。它也与SDC顾问毫不费力地创建初始的约束。
 
关于Cadence
Cadence公司成就全球电子设计创新,并在创建当今集成电路和电子产品中发挥核心作用。我们的客户采用Cadence的软件,硬件,设计方法和服务,来设计和验证尖端半导体器件,消费电子产品,网络和通讯设备以及计算机系统。 Cadence公司公布的约16十亿$ 2007年的收入,并拥有约5100名员工。该公司总部设在加利福尼亚州圣何塞市均设有销售办事处,设计中心和研究设施,在世界各地以服务于全球电子产业。

 

Cadence Design Systems, Inc., the leader in global electronic design innovation, has released 15.20 version of CONFORMAL. This technologies provide you with an independent equivalence checking solution enabling verification of designs from RTL to final netlists from P&R.
 
In addition to standard equivalence checking, the Conformal solution offers:
 
- Static verification solutions for low-power designs, including low power-aware equivalency checking
- Automated ECO generation capabilities for minimal netlist changes and faster tapeouts
- Constraint designer for clock domain crossing and SDC verification solutions
 
Cadence Conformal Constraint Designer provides a complete and efficient path to develop and manage constraints and clock-domain crossings (CDCs), ensuring they are functionally correct from RTL to layout. By pinpointing real design issues quickly and accurately, delivering higher quality timing constraints, and finding issues with clock-domain synchronizers, the solution helps you reduce overall design cycle times and enhance quality of silicon in complex SoC designs.
 
With Conformal Constraint Designer, you can reduce the risk of respins through formal validation of constraints. Since the solution quickly validates failing timing paths as functionally false, it speeds convergence for timing closure. It also creates initial constraints effortlessly with the SDC advisor.
 
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2007 revenues of approximately $1.6 billion, and has approximately 5,100 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
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